DBPapers
DOI: 10.5593/SGEM2014/B21/S7.026

HARDWARE VIOLATION MONITOR OF TRANSACTION LEVEL REAL-TIME CONSTRAINTS FOR RELIABLE SYSTEMS ON A CHIP

P. Kustarev, S. Bikovsky, V. Pinkevich
Wednesday 1 October 2014 by Libadmin2014

References: 14th International Multidisciplinary Scientific GeoConference SGEM 2014, www.sgem.org, SGEM2014 Conference Proceedings, ISBN 978-619-7105-10-0 / ISSN 1314-2704, June 19-25, 2014, Book 2, Vol. 1, 201-208 pp

ABSTRACT
The paper deals with hard real-time constraints issue while developing reliable systems on chip (SoC). The emphasis is focused on evaluation of time constraints monitoring approaches at the chip prototyping stage (FPGA or ASIC). The authors propose a new method of real-time constraints formal description at the transaction level. The hardware violation monitor based on the proposed approach has been developed and results of its experimental implementation are shown in the article. This monitor is possible to be implemented in SoCs based on such common bus architectures like AMBA, OCP and WISHBONE.

Keywords: SoC, real-time constraints, hardware checkers, temporal logic, model checking.

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